Intel® Xeon Phi™ Coprocessor
Developer Training Event
Chicago, IL

Event Details:

Tuesday, July 22, 2014
Registration Begins: 8:30AM 
Presentation: 9:00AM to 4:00PM 
Lunch will be provided.

University of Chicago
Joseph Regenstein Library
1100 E 57th Street
Chicago, IL 60637 

Arrival: The meeting will take place in JRL 122, located at the west end of the Regenstein 1st Floor outer lobby.

Please complete a very brief pre-training questionnaire at the following URL: 
http://www.colfax-intl.com/nd/svy.aspx?rord

This one-day training will provide software developers the foundation needed for modernizing their code to take advantage of parallel architectures found in both the Intel® Xeon® processor and the Intel® Xeon Phi™ coprocessor.

The session will cover:

• An overview of parallel programming frameworks and optimization guidelines for multi-core CPUs (Intel® Xeon®) and many-core coprocessors (Intel® Xeon Phi™):
• Discussions about three layers of parallelism: SIMD, Threads, Cluster environment
• Tips for quick porting/development of HPC software applications
• Real-life examples of code and optimization techniques
• Hardware solution and corresponding software implementations, APIs, and framework

Register Now! 

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